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ltc3612 3612fa typical a pplica t ion fea t ures a pplica t ions descrip t ion 3a, 4mhz monolithic synchronous step-down dc/dc converter the ltc ? 3612 is a low quiescent current monolithic syn - chronous buck regulator using a current mode, constant frequency architecture. the no-load dc supply current in sleep mode is only 70a while maintaining the output voltage (burst mode operation) at no load, dropping to zero current in shutdown. the 2.25v to 5.5v input supply voltage range makes the ltc3612 ideally suited for single li-ion as well as fixed low voltage input applications. 100% duty cycle capability provides low dropout operation, extending the operating time in battery-powered systems. the operating frequency is externally programmable up to 4mhz, allowing the use of small surface mount inductors. for switching noise-sensitive applications, the ltc3612 can be synchronized to an external clock at up to 4mhz. forced continuous mode operation in the ltc3612 reduces noise and rf interference. adjustable compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the internal synchronous switch increases efficiency and eliminates the need for an external catch diode, saving external components and board space. the ltc3612 is offered in a leadless 20-pin 3mm 4mm qfn or a thermally enhanced 20-pin tssop package. efficiency and power loss vs load current n 3a output current n 2.25v to 5.5v input voltage range n low output ripple burst mode ? operation: i q = 70a n 1% output voltage accuracy n output voltage down to 0.6v n high efficiency: up to 95% n low dropout operation: 100% duty cycle n shutdown current: 1a n adjustable switching frequency: up to 4mhz n optional active voltage positioning (avp) with internal compensation n selectable pulse-skipping/forced continuous/ burst mode operation with adjustable burst clamp n programmable soft-start n inputs for start-up tracking or external reference n ddr memory mode, i out = 1.5a n available in thermally enhanced 20-pin (3mm 4mm) qfn and tssop packages n point-of-load supplies n distributed power supplies n portable computer systems n ddr memory termination n handheld devices l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6580258, 5481178, 5994885, 6304066, 6498466, 6611131. run track/ss rt/sync pgood ith sgnd pgnd v in 2.5v to 5.5v pv i n _drv ddr sv in ltc3612 sw pv in 560nh 665k 210k 3612 ta01a 22f s 2 mode v fb 47f v out 2.5v 3a output current (ma) 30 efficiency (%) power loss (w) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3612 ta01b 0 10 0.001 1 0.1 0.01 10 v in = 5v v in = 3.3v v in = 2.8v
ltc3612 3612fa a bsolu t e maxi m u m r a t ings pv in , sv in , pv in_drv voltages ..................... C0.3v to 6v sw voltage .................................. C0.3v to (pv in + 0.3v) ith, rt/sync voltages ............... C0.3v to (sv in + 0.3v) ddr, track/ss voltages ........... C0.3v to (sv in + 0.3v) mode, run, v fb voltages .......... C0.3v to (sv in + 0.3v) pgood voltage ............................................ C0.3v to 6v (notes 1, 11) 20 19 18 17 7 8 top view 21 udc package 20-lead (3mm s 4mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 ddr r t /sync sgnd nc sw sw pgood run sv in pv in_drv sw sw track/ss ith v fb mode nc pv in pv in nc t jmax = 125c, ja = 43c/w exposed pad (pin 21) is pgnd, must be soldered to pcb fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 sv in run pgood mode v fb ith track/ss ddr r t /sync sgnd pv in_drv sw nc sw pv in pv in sw nc sw nc 21 t jmax = 125c, ja = 38c/w exposed pad (pin 21) is pgnd, must be soldered to pcb p in c on f igura t ion or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3612eudc#pbf ltc3612eudc#trpbf ldqt 20-lead (3mm 4mm) plastic qfn C40c to 125c ltc3612iudc#pbf ltc3612iudc#trpbf ldqt 20-lead (3mm 4mm) plastic qfn C40c to 125c ltc3612efe#pbf ltc3612efe#trpbf ltc3612fe 20-lead plastic tssop C40c to 125c ltc3612ife#pbf ltc3612ife#trpbf ltc3612fe 20-lead plastic tssop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 2, 11) .......................................... C40c to 125c storage temperature .............................. C65c to 150c reflow peak body temperature (qfn) .................. 260c lead temperature (soldering, 10 sec) tssop .............................................................. 300c
ltc3612 3612fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 3.3v, rt/sync = sv in , unless otherwise specified (note 2). symbol parameter conditions min typ max units v in operating voltage range l 2.25 5.5 v v uvlo undervoltage lockout threshold sv in ramping down sv in ramping up l l 1.7 2.25 v v v fb feedback voltage internal reference (notes 3, 4) v track/ss = sv in , v ddr = 0v 0c < t j < 85c C40c < t j < 125c l 0.594 0.591 0.6 0.606 0.609 v v feedback voltage external reference (note 7) (notes 3, 4) v track/ss = 0.3v, v ddr = sv in 0.289 0.3 0.311 v (notes 3, 4) v track/ss = 0.5v, v ddr = sv in 0.489 0.5 0.511 v i fb feedback input current v fb = 0.6v l 30 na ? v linereg line regulation sv in = pv in = 2.25v to 5.5v (notes 3, 4) track/ss = sv in l 0.2 %/v ? v loadreg load regulation ith from 0.5v to 0.9v (notes 3, 4) v ith = sv in (note 5) 0.25 2.6 % % i s active mode v fb = 0.5v, v mode = sv in (note 6) 1100 a sleep mode v fb = 0.7v, v mode = 0v, ith = sv in (note 5) 70 100 a v fb = 0.7v, v mode = 0v (note 4) 120 160 a shutdown sv in = pv in = 5.5v, v run = 0v 0.1 1 a r ds(on) top switch on-resistance pv in = 3.3v (note 10) 70 m bottom switch on-resistance pv in = 3.3v (note 10) 45 m i lim top switch current limit sourcing (note 8), v fb = 0.5v duty cycle <35% duty cycle = 100% 5.2 4 6 6.8 a a bottom switch current limit sinking (note 8), v fb = 0.7v, forced continuous mode C3 C4 C5 a g m(ea) error amplifier transconductance C5a < i ith < 5a (note 4) 200 s i eao error amplifier max output current (note 4) 30 a t ss internal soft-start time v fb from 0.06v to 0.54v, track/ss = sv in 0.65 1 1.5 ms v track/ss enable internal soft-start (note 7 ) 0.62 v t track/ss_dis soft-start discharge time at start-up 70 s r on(track/ss_dis) track/ss pull-down resistor at start-up 200 f osc oscillator frequency rt/sync = 370k l 0.8 1 1.2 mhz internal oscillator frequency v rt/sync = sv in l 1.8 2.25 2.7 mhz f sync synchronization frequency 0.3 4 mhz v rt/sync sync level high 1.2 v sync level low . 0.3 v i sw(lkg) switch leakage current sv in = pv in = 5.5v, v run = 0v 0.1 1 a v ddr ddr option enable voltage sv in C 0.3 v v mode (note 9) internal burst mode operation 0.3 v pulse-skipping mode sv in C 0.3 v forced continuous mode 1.1 sv in ? 0.58 v external burst mode operation 0.45 0.8 v
ltc3612 3612fa efficiency vs load current (v mode = 0v) efficiency vs load current (v mode = 0v) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3612 is tested under pulsed load conditions such that t j t a . the ltc3612e is guaranteed to meet performance specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3612i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 3.3v, rt/sync = sv in , unless otherwise specified (note 2). symbol parameter conditions min typ max units pgood power good voltage windows track/ss = sv in , entering window v fb ramping up v fb ramping down C3.5 3.5 C6 6 % % track/ss = sv in , leaving window v fb ramping up v fb ramping down 9 C9 11 C11 % % t pgood power good blanking time entering and leaving window 70 105 140 s r pgood power good pull-down on-resistance 8 17 33 v run run voltage input high input low l l 1 0.4 v v note 3: this parameter is tested in a feedback loop which servos v fb to t he midpoint for the error amplifier (v ith = 0.75v). note 4: external compensation on ith pin. note 5: tying the ith pin to sv in enables the internal compensation and avp mode. note 6: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 7: see description of the track/ss pin in the pin functions section. note 8: in sourcing mode the average output current is flowing out of sw pin. in sinking mode the average output current is flowing into the sw pin. note 9: see description of the mode pin in the pin functions section. note 10: guaranteed by correlation and design to wafer level measurements for qfn packages. note 11: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. typical p er f or m ance c harac t eris t ics output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3612 g01 0 10 v in = 5v v in = 3.3v v in = 2.5v v out = 1.8v output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3612 g02 0 10 v in = 5v v in = 3.3v v in = 2.5v v out = 1.2v v in = 3.3v, rt/sync = sv in , unless otherwise noted.
ltc3612 3612fa typical p er f or m ance c harac t eris t ics efficiency vs load current efficiency vs input voltage (v mode = 0v) efficiency vs frequency (v mode = 0v), i out = 1a load regulation line regulation burst mode operation pulse-skipping mode operation forced continuous mode operation output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3612 g03 0 10 burst mode external clamp = 0.7v burst mode internal clamp pulse- skipping mode forced continuous mode v out = 1.8v input voltage (v) 2.25 30 efficiency (%) 40 60 70 80 100 3612 g04 50 90 3.75 3.25 5.25 2.75 4.25 4.75 i out = 3ma i out = 300ma i out = 1a i out = 3a v out = 1.8v frequency (mhz) 0.5 82 efficiency (%) 83 84 85 86 95 89 91 93 94 92 88 90 1.0 1.5 2.0 3.0 2.5 3.5 3612 g05 4.0 4.5 87 1h 0.68h 0.33h v out = 1.8v output current (ma) 0 ?0.3 v out error (%) ?0.1 0.3 0.5 0.7 2000 1.5 3612 g06 0.1 1000 500 2500 1500 3000 0.9 1.1 1.3 forced continuous mode internal burst mode operation pulse-skipping mode v out = 1.8v input voltage (v) 2.20 ?0.3 v out error (%) ?0.2 ?0.1 0 0.1 0.3 2.75 3.30 3.85 4.40 3612 g07 4.95 5.50 0.2 v out 20mv/div i l 500ma/div 20s/div 3612 g08 v out = 1.8v i out = 75ma v mode = 0v v out 20mv/div i l 500ma/div 20s/div 3612 g09 v out = 1.8v i out = 75ma v mode = 3.3v v out 20mv/div i l 200ma/div 1s/div 3612 g10 v out = 1.8v i out = 100ma v mode = 1.5v v in = 3.3v, rt/sync = sv in , unless otherwise noted.
ltc3612 3612fa sinking current load step transient in forced continuous mode without avp mode load step transient in forced continuous mode with avp mode load step transient in forced continuous mode sourcing and sinking current v out 200mv/div i l 1a/div 50s/div 3612 g13 v out = 1.8v i load = 100ma to 3a v mode = 1.5v compensation figure 1 v out 100mv/div i l 1a/div 50s/div 3612 g14 v out = 1.8v i load = 100ma to 3a v mode = 1.5v v ith = v in output capacitor value figure 1 v out 200mv/div i l 2a/div 0a 50s/div 3612 g15 v out = 1.8v i load = ?1.5a to 3a v mode = 1.5v compensation figure 1 v out 20mv/div sw 2v/div i l 500ma/div 1s/div 3612 g16 v out = 1.2v i out = ?1a v mode = 1.5v typical p er f or m ance c harac t eris t ics v in = 3.3v, rt/sync = sv in , unless otherwise noted. load step transient in pulse-skipping mode load step transient in burst mode operation v out 200mv/div i l 1a/div 50s/div 3612 g11 v out = 1.8v i load = 100ma to 3a v mode = 3.3v compensation figure 1 v out 200mv/div i l 1a/div 50s/div 3612 g12 v out = 1.8v i load = 100ma to 3a v mode = 0v compensation figure 1
ltc3612 3612fa internal start-up in forced continuous mode tracking up/down in forced continuous mode, ddr pin tied to 0v tracking up/down in forced continuous mode, ddr pin tied to sv in reference voltage vs temperature switch on-resistance vs input voltage v out 500mv/div run 1v/div i l 1a/div pgood 2v/div 500s/div 3612 g17 v out = 1.8v i out = 3a v mode = 1.5v v out 1v/div v track/ss 500mv/div pgood 2v/div 2ms/div 3612 g18 v out = 0v to 1.8v i out = 3a v track/ss = 0v to 0.7v v mode = 1.5v v ddr = 0v v track/ss 200mv/div v out 500mv/div pgood 2v/div 2ms/div 3612 g19 v out = 0v to 1.2v i out = 3a v track/ss = 0v to 0.4v v mode = 1.5v v ddr = 3.3v temperature (c) ?50 0.594 reference voltage (v) 0.596 0.600 0.602 0.604 ?10 30 50 130 3612 g20 0.598 ?30 10 70 90 110 0.606 input voltage (v) 2.5 r ds(0n) () 0.06 0.08 0.10 4.5 3612 g21 0.04 0.02 0.05 0.07 0.09 0.03 0.01 0 3.0 3.5 4.0 5.0 5.5 main switch synchronous switch switch on-resistance vs temperature temperature (c) ?50 0 r ds(on) () 0.01 0.03 0.04 0.05 70 0.09 3612 g22 0.02 10 ?10 110 50 ?30 90 30 130 0.06 0.07 0.08 main switch synchronous switch typical p er f or m ance c harac t eris t ics v in = 3.3v, rt/sync = sv in , unless otherwise noted.
ltc3612 3612fa frequency vs input voltage switch leakage vs temperature, main switch switch leakage vs temperature, synchronous switch frequency vs resistor on rt/sync pin frequency vs temperature dynamic supply current vs input voltage without avp mode resistor on rt/sync pin (k) 0 0 frequency (khz) 500 1500 2000 2500 800 4500 3612 g23 1000 400 200 1000 1200 600 1400 3000 3500 4000 temperature (c) ?50 ?1.2 frequency variation (%) ?1.0 ?0.6 ?0.4 ?0.2 0.8 0.2 ?10 30 50 130 3612 g24 ?0.8 0.4 0.6 0 ?30 10 70 90 100 input voltage (v) 2.25 ?2.5 frequency variation (%) ?2.0 ?1.0 ?0.5 0 1.0 3612 g25 ?1.5 0.5 3.75 3.25 5.25 2.75 4.25 4.75 temperature (c) ?50 switch leakage (na) 2000 2500 3000 110 3612 g26 1500 1000 0 ?10 30 70 ?30 130 10 50 90 500 4000 3500 v in = 2.25v v in = 3.3v v in = 5.5v temperature (c) ?50 switch leakage (na) 2000 2500 3000 110 3612 g27 1500 1000 0 ?10 30 70 ?30 130 10 50 90 500 4000 3500 v in = 2.25v v in = 3.3v v in = 5.5v input voltage (v) 0.1 dynamic supply current (ma) 1 10 100 2.25 3.25 3.75 4.25 4.75 0.01 2.75 5.25 3612 g28 forced continuous mode pulse-skipping mode burst mode operation typical p er f or m ance c harac t eris t ics v in = 3.3v, rt/sync = sv in , unless otherwise noted.
ltc3612 3612fa v out short to gnd, forced continuous mode dynamic supply current vs temperature without avp mode temperature (c) 0.1 dynamic supply current (ma) 1 10 100 ?50 30 70 110 130 0.01 ?10 10 50 90 ?30 3612 g29 forced continuous mode pulse-skipping mode burst mode operation v out 1v/div i l 2a/div 50s/div 3612 g30 v out = 2.5v i out = 0a v mode = 1.5v start-up from shutdown with prebiased output (forced continuous mode) output voltage during sinking vs input voltage v out 500mv/div pgood 5v/div i l 2a/div 20s/div 3612 g31 prebiased v out = 2.2v v out = 1.2v i out = 0a v mode = 1.5v input voltage (v) 2.25 1.76 v out (v) 1.78 1.82 1.84 1.86 1.90 3612 g32 1.80 1.88 3.75 3.25 5.25 2.75 4.25 4.75 ?1.5a, 2mhz, 120c ?1.5a, 2mhz, 25c v out = 1.8v 1h inductor output voltage during sinking vs input voltage input voltage (v) 2.25 0.88 v out (v) 0.89 0.91 0.92 0.93 0.95 3612 g33 0.90 0.94 3.75 3.25 5.25 2.75 4.25 4.75 ?1.5a, 1mhz, 120c ?1.5a, 1mhz, 25c v out = 0.9v 1h inductor typical p er f or m ance c harac t eris t ics v in = 3.3v, rt/sync = sv in , unless otherwise noted.
ltc3612 0 3612fa p in func t ions (qfn/fe) ddr (pin 1/pin 8): ddr mode pin. tying the ddr pin to sv in selects ddr mode and track/ss can be used as an external reference input. if ddr is tied to sgnd, the internal 0.6v reference will be used. rt/sync (pin 2/pin 9): oscillator frequency. this pin provides three ways of setting the constant switching frequency: 1. connecting a resistor from rt/sync to ground will set the switching frequency based on the resistor value. 2. driving the rt/sync pin with an external clock signal will synchronize the ltc3612 to the applied frequency. the slope compensation is automatically adapted to the external clock frequency. 3. tying the rt/sync pin to sv in enables the internal 2.25mhz oscillator frequency. sgnd (pin 3/pin 10): signal ground. all small-signal and compensation components should connect to this ground, which in turn should connect to pgnd at a single point. nc (pins 4, 7, 10/pins 11, 13, 18): can be connected to ground or left open. sw (pins 5, 6, 11, 12/pins 12, 14, 17, 19): switch node. connection to the inductor. this pin connects to the drains of the internal synchronous power mosfet switches. pv in (pins 8, 9/pins 15, 16): power input supply. pv in connects to the source of the internal p-channel power mosfet. this pin is independent of sv in and may be con - nected to the same voltage or to a lower voltage supply. pv in_drv (pin 13/pin 20): internal gate driver input sup - ply. this pin must be connected to pv in . sv in (pin 14/pin 1): signal input supply. this pin pow - ers the internal control circuitry and is monitored by the undervoltage lockout comparator. run (pin 15/pin 2): enable pin. forcing this pin to ground shuts down the ltc3612. in shutdown, all functions are disabled and the chip draws <1a of supply current. pgood (pin 16/pin 3): power good. this open-drain output is pulled down to sgnd on start-up and while the fb voltage is outside the power good voltage window. if the fb voltage increases and stays inside the power good window for more than 105s the pgood pin is released. if the fb voltage leaves the power good window for more than 105s the pgood pin is pulled down. in ddr mode (ddr = v in ), the power good window moves in relation to the actual track/ss pin voltage. during up/ down tracking the pgood pin is always pulled down. in shutdown the pgood output will actively pull down and may be used to discharge the output capacitors via an external resistor. mode (pin 17/pin 4): mode selection. tying the mode pin to sv in or sgnd enables pulse-skipping mode or burst mode operation (with an internal burst mode clamp), respectively. if this pin is held at slightly higher than half of sv in , forced continuous mode is selected. connecting this pin to an external voltage selects burst mode opera - tion with the burst clamp set to the pin voltage. see the operation section for more details. v fb (pin 18/pin 5): voltage feedback input pin. senses the feedback voltage from the external resistive divider across the output. ith (pin 19/pin 6): error amplifier compensation. the current comparators threshold increases with this control voltage. tying this pin to sv in enables internal compensa - tion and avp mode. track/ss (pin 20/pin 7): track/external soft-start/ex - ternal reference. start-up behavior is programmable with the track/ss pin: 1. tying this pin to sv in selects the internal soft-start circuit. 2. external soft-start timing can be programmed with a capacitor to ground and a resistor to sv in . 3. track/ss can be used to force the ltc3612 to track the start-up behavior of another supply. the pin can also be used as external reference input. see the applications information section for more information. pgnd (pin 21/pin 21): power ground. the exposed pad connects to the source of the internal n-channel power mosfet. this pin should be connected close to the (C) terminal of c in and c out and soldered to pcb ground for rated thermal performance.
ltc3612 3612fa f unc t ional b lock diagra m ? + ? + ? + ? + ? + ? + mode + sleep mode burst comparator ith sense comparator error amplifier foldback amplifier 0.6v 0.3v r 0.555v track/ss 0.645v ddr exposed pad 3612 bd soft-start bandgap and bias ? + ? + v fb run sgnd rt/sync ith sv in ? 0.3v pv in pv in_drv sv in pgood logic sw sw sw sw pgnd reverse comparator i rev oscillator ? + internal compensation current sense slope compensation pmos current comparator ith limit driver
ltc3612 3612fa mode selection the mode pin is used to select one of four different operating modes: o pera t ion main control loop the ltc3612 is a monolithic, constant frequency, current mode step-down dc/dc converter. during normal opera - tion, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power switch. the peak inductor cur - rent at which the current comparator trips is controlled by the voltage on the ith pin. the error amplifier adjusts the voltage on the ith pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.6v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the ith voltage until the average inductor current matches the new load current. typical voltage range for the ith pin is from 0.1v to 1.05v with 0.45v corresponding to zero current. when the top power switch shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the next clock cycle begins. the bottom current limit is typically set at C4a for forced continuous mode and 0a for burst mode operation and pulse-skipping mode. the operating frequency defaults to 2.25mhz when rt/sync is connected to sv in , or can be set by an external resistor connected between the rt/sync pin and ground, or by a clock signal applied to the rt/sync pin. the switch - ing frequency can be set from 300khz to 4mhz. overvoltage and undervoltage comparators pull the pgood output low if the output voltage varies typically more than 7.5% from the set point. ps pulse-skipping mode enable forced continuous mode enable burst mode enable?internal clamp 3612 op01 burst mode enable?external clamp, controlled by voltage applied at mode pin sv in sv in ? 0.3v sv in ? 0.58 1.1v 0.8v 0.45v 0.3v sgnd bm bm ext fc mode selection voltage burst mode operationinternal clamp connecting the mode pin to sgnd enables burst mode operation with an internal clamp. in burst mode operation the internal power switches operate intermittently at light loads. this increases efficiency by minimizing switching losses. during the intervals when the switches are idle, the ltc3612 enters sleep state where many of the internal circuits are disabled to save power. during burst mode operation, the minimum peak inductor current is internally clamped and the voltage on the ith pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the ith pin drops. as the ith voltage falls below the internal clamp, the burst comparator trips and enables sleep mode. dur - ing sleep mode, the power mosfets are held off and the load current is solely supplied by the output capacitor. when the output voltage drops, the top power switch is turned back on and the internal circuits are re-enabled. this process repeats at a rate that is dependent on the load current.
ltc3612 3612fa o pera t ion burst mode operationexternal clamp connecting the mode pin to a voltage in the range of 0.45v to 0.8v enables burst mode operation with external clamp. during this mode of operation the minimum voltage on the ith pin is externally set by the voltage on the mode pin. it is recommended to use burst mode operation with an internal clamp for temperatures above 85c ambient. pulse-skipping mode operation pulse-skipping mode is similar to burst mode operation, but the ltc3612 does not disable power to the internal circuitry during sleep mode. this improves output voltage ripple but uses more quiescent current, compromising light load efficiency. tying the mode pin to sv in enables pulse-skipping mode. as the load current decreases, the peak inductor current will be determined by the voltage on the ith pin until the ith voltage drops below the voltage level corresponding to 0a. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on- time inductor current, switching cycles will be skipped to keep the output voltage in regulation. forced continuous mode in forced continuous mode the inductor current is con - stantly cycled which creates a minimum output voltage ripple at all output current levels. connecting the mode pin to a voltage in the range of 1.1v to sv in ? 0.58 will enable forced continuous mode operation. at light loads, forced continuous mode operation is less efficient than burst mode or pulse-skipping operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of the signal band. forced continuous mode must be used if the output is required to sink current. dropout operation as the input supply voltage approaches the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3612 is designed to operate down to an input supply voltage of 2.25v. an important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3612 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. see the typical perfor - mance characteristics graphs. short-circuit protection the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ith pin. if the output current increases, the error amplifier raises the ith pin voltage until the average inductor current matches the new load current. in normal operation the ltc3612 clamps the maximum ith pin voltage at approximately 1.05v which corresponds typically to 6a peak inductor current. when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. the ltc3612 uses two techniques to prevent current runaway from occurring.
ltc3612 3612fa a pplica t ions i n f or m a t ion if the output voltage drops below 50% of its nominal value, the clamp voltage at ith pin is lowered causing the maxi - mum peak inductor current to decrease gradually with the output voltage. when the output voltage reaches 0v the clamp voltage at the ith pin drops to 40% of the clamp voltage during normal operation. the short-circuit peak inductor current is determined by the minimum on-time of the ltc3612, the input voltage and the inductor value. this foldback behavior helps in limiting the peak inductor current when the output is shorted to ground. it is disabled during internal or external soft-start and tracking up/down operation (see the applications information section). a secondary limit is also imposed on the valley inductor current. if the inductor current measured through the bottom mosfet increases beyond 6a typical, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. o pera t ion the basic ltc3612 application circuit is shown in figure 1. operating frequency selection of the operating frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3612 is determined by an external resistor that is connected between the rt/sync pin and ground. the value of the resistor sets run track/ss rt/sync pgood ith sgnd pgnd v in 2.25v to 5.5v pv i n _drv ddr sv in ltc3612 sw pv in c in1 22f c c 470pf c ss 22nf l1 470nh r1 392k r2 196k 3612 f01 c in2 22f mode v fb c out1 47f c out2 22f v out 1.8v 3a r c 15k r t 130k r ss 2m c c1 10pf (opt) figure 1. 1.8v, 3a step-down regulator the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r t = 3 . 8 2 ? 1 0 1 1 h z f o s c h z ( ) ? ? 1 6 k ? although frequencies as high as 4mhz are possible, the minimum on-time of the ltc3612 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 60ns; therefore, the minimum duty cycle is equal to 100 ? 60ns ? f osc (hz)%. tying the rt/sync pin to sv in sets the default internal operating frequency to 2.25mhz 20%.
ltc3612 3612fa a pplica t ions i n f or m a t ion frequency synchronization the ltc3612s internal oscillator can be synchronized to an external frequency by applying a square wave clock signal to the rt/sync pin. during synchronization, the top switch turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300khz to 4mhz. during synchronization all operation modes can be selected. it is recommended that the regulator is powered down (run pin to ground) before removing the clock signal on the rt/sync pin in order to reduce inductor current ripple. ac coupling should be used if the external clock genera - tor cannot provide a continuous clock signal throughout start-up, operation and shutdown of the ltc3612. the size of capacitor c sync depends on parasitic capacitance on the rt/sync pin and is typically in the range of 10pf to 22pf inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current ? i l increases with higher v in and decreases with higher inductance: ? i l = v o u t f s w ? l ? ? ? ? ? ? ? 1 ? v o u t v i n ? ? ? ? ? ? having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors and the output voltage ripple. a reasonable starting point for selecting the ripple current is ? i l = 0.3 ? i out(max) . the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l = v o u t f s w ? ? i l ( m a x ) ? ? ? ? ? ? ? 1 ? v o u t v i n ? ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low cur - rent operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for fixed inductor value, but it is very dependent on the induc - tance selected. as the inductance increases, core losses de - crease. unfortunately, increased inductance requires more turns of wire and therefore, copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, meaning that inductance collapses abruptly when the peak design current is ex - ceeded. this results in an abrupt increase in inductor ltc3612 sv in v in r t /sync ltc3612 sv in v in 0.4v r t /sync r t r t sgnd ltc3612 sv in f osc 2.25mhz f osc 1/t p f osc t 1/ r t v in r t /sync sgnd t p 1.2v 0.3v ltc3612 sv in f osc 1/t p v in c sync r t /sync sgnd 3612 f02 figure 2. setting the switching frequency
ltc3612 3612fa a pplica t ions i n f or m a t ion ripple current and consequently output voltage ripple. do not allow a ferrite core to saturate! different core materials and shapes will change the size/cur - rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. table 1 shows some typical surface mount inductors that work well in ltc3612 applications. input capacitor (c in ) selection in continuous mode, the source current of the top p-chan - nel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used at v in . the maximum rms capacitor current is given by: i r m s = i o u t ( m a x ) ? v o u t v i n ? v i n v o u t ? 1 ? ? ? ? ? ? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. output capacitor (c out ) selection the selection of c out is typically driven by the required esr to minimize voltage ripple and load step transients (low esr ceramic capacitors are discussed in the next section). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ? v out is determined by: ? v o u t ? i l ? e s r + 1 8 ? f s w ? c o u t ? ? ? ? ? ? table 1. representative surface mount inductors inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) vishay ihlp-2525ah-01 series 0.33 7 12 6.7 7 1.8 0.47 9 11 6.7 7 1.8 0.68 13 9 6.7 7 1.8 0.82 15 8 6.7 7 1.8 1.0 18 7 6.7 7 1.8 vishay ihlp-1616bz-01 series 0.22 8 24 4.3 4.7 2 0.47 18 11.5 4.3 4.7 2 1.00 37 8.5 4.3 4.7 2 sumida cdmc6d28 series 0.3 3.2 15.4 6.7 7.25 3 0.47 4.2 13.6 6.7 7.25 3 0.68 5.4 11.3 6.7 7.25 3 1 8.8 8.8 6.7 7.25 3 nec/tokin mplc0730l series 0.47 4.5 16.6 6.9 7.7 3.0 0.75 7.5 12.2 6.9 7.7 3.0 1.0 9.0 10.6 6.9 7.7 3.0 cooper hcp0703 series 0.22 2.8 23 7 7.3 3.0 0.47 4.2 17 7 7.3 3.0 0.68 5.5 15 7 7.3 3.0 0.82 8.0 13 7 7.3 3.0 1.0 10.0 11 7 7.3 3.0 1.5 9.6 61 6.9 7.3 3.2 wrth elektronik we-hc744312 series 0.25 2.5 18 7 7.7 3.8 0.47 3.4 16 7 7.7 3.8 0.72 7.5 12 7 7.7 3.8 1.0 9.5 11 7 7.7 3.8 1.5 10.5 9 7 7.7 3.8 coilcraft do1813h series 0.33 4 10 8.9 6.1 5 0.56 10 7.7 8.9 6.1 5 coilcraft v series 0.27 0.1 14 7.5 6.7 3 0.35 0.1 11 7.5 6.7 3 0.4 0.1 8 7.5 6.7 3
ltc3612 3612fa a pplica t ions i n f or m a t ion where f osc = operating frequency, c out = output capaci - tance and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. tantalum capacitors have the highest capacitance density, but can have higher esr and must be surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can often be used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic input and output capacitors ceramic capacitors have the lowest esr and can be cost effective, but also have the lowest capacitance density, high voltage and temperature coefficients, and exhibit audible piezoelectric effects. in addition, the high-q of ceramic capacitors along with trace inductance can lead to significant ringing. they are attractive for switching regulator use because of their very low esr, but great care must be taken when using only ceramic input and output capacitors. ceramic capacitors are prone to temperature effects which require the designer to check loop stability over the operating temperature range. to minimize their large temperature and voltage coefficients, only x5r or x7r ceramic capacitors should be used. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensa - tion components and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 4 times the linear drop of the first cycle; however, this behavior can vary depending on the compensation component values. thus, a good place to start is with the output capacitor size of approximately: c o u t 3 . 5 ? ? i o u t f s w ? v d r o o p this is only an approximation; more capacitance may be needed depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. output voltage programming the output voltage is set by an external resistive divider according to the following equation: v o u t = 0 . 6 ? 1 + r 1 r 2 ? ? ? ? ? ? v the resistive divider allows pin v fb to sense a fraction of the output voltage, as shown in figure 1. burst clamp programming if the voltage on the mode pin is less than 0.8v, burst mode operation is enabled. if the voltage on the mode pin is less than 0.3v, the internal default burst clamp level is selected. the minimum voltage on the ith pin is typically 525mv (internal clamp). if the voltage is between 0.45v and 0.8v, the voltage on the mode pin (v burst ) is equal to the minimum voltage on the ith pin (external clamp) and determines the burst clamp level i burst (typically from 0a to 3.5a).
ltc3612 3612fa when the ith voltage falls below the internal (or external) clamp voltage, the sleep state is enabled. as the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is greater than the output load current, the voltage on the ith pin will decrease. when the ith voltage drops, sleep mode is enabled in which both power switches are shut off along with most of the circuitry to minimize power consumption. all circuitry is turned back on and the power switches resume opera - tion when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple increase. note that for very high v burst voltage settings, the power good comparator may trip, since the output ripple may get bigger than the power good window. pulse-skipping mode, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting mode to sv in . this sets i burst to 0a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator. the lowest output voltage ripple is achieved while still operating discontinuously. during very light output loads, pulse skipping allows only a few switching cycles to skip while maintaining the output voltage in regulation. internal and external compensation the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc load current. when a load step occurs, v out shifts by an amount equal to ? i load(esr) , where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out , generating the feedback error signal that forces the regula - tor to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin allows the transient response to be optimized over a wide range of output capacitance. the ith external components (r c and c c ) shown in fig - ure 1 provide adequate compensation as a starting point for most applications. the values can be modified slightly to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. the gain of the loop will be in - creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system. the external capaci - tor, c c1 , (figure 1) is not needed for loop stability, but it helps filter out any high frequency noise that may couple onto that node. the general purpose buck regulator ap - plication in the typical applications section uses a faster compensation to improve load step response. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. more output capacitance may be required depending on the duty cycle and load step requirements. avp mode fast load transient response, limited board space and low cost are typical requirements of microprocessor power supplies. a microprocessor has typical full load step with very fast slew rate. the voltage at the microprocessor must be held to about 0.1v of nominal in spite of these load current steps. since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. normally, several capacitors in parallel are required to meet microprocessor transient requirements. capacitor a pplica t ions i n f or m a t ion
ltc3612 3612fa esr and esl primarily determine the amount of droop or overshoot in the output voltage. consider the ltc3612 without avp with a bank of tantalum output capacitors. if a load step with very fast slew rate occurs, the voltage excursion will be seen in both direc - tions, for full load to minimum load transient and for the minimum load to full load transient. if the ith pin is tied to sv in , the active voltage positioning (avp) mode and internal compensation are selected. avp mode intentionally compromises load regulation by reducing the gain of the feedback circuit, resulting in an output voltage that varies with load current. when the load current suddenly increases, the output voltage starts from a level slightly higher than nominal so the output voltage can droop more and stay within the specified voltage range. when the load current suddenly decreases the output voltage starts at a level lower than nominal so the a pplica t ions i n f or m a t ion figure 4. load step transient forced continuous mode with avp mode output voltage can have more overshoot and stay within t he specified voltage range (see figures 3 and 4). the benefit is a lower peak-to-peak output voltage deviation for a given load step without having to increase the output filter capacitance. alternatively, the output voltage filter ca - pacitance can be reduced while maintaining the same peak to peak transient response. due to the reduced loop gain in avp mode, no external compensation is required. ddr mode the ltc3612 can both source and sink current if the mode pin is configured to forced continuous mode. current sinking is typically limited to 1.5a, for 1mhz frequency and a 1h inductor, but can be lower at higher frequencies and low output voltages. if higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. see the typical performance charac - teristics curves for more information. in addition, tying the ddr pin to sv in , lower external reference voltage and tracking output voltage between channels are possible. see the output voltage tracking and external reference input sections. soft-start the run pin provides a means to shut down the ltc3612. tying the run pin to sgnd places the ltc3612 in a low quiescent current shutdown state (i q < 1a). the ltc3612 is enabled by pulling the run pin high. however, the applied voltage must not exceed sv in . in some applications, the run signal is generated within another power domain and is driven high while the sv in and pv in is still 0v. in this case, its required to limit the current into the run pin by either adding a 1m resistor or a 100k resistor, plus a schottky diode, to sv in . after pulling the run pin high, the chip enters a soft start-up state. this type of soft start-up behavior is set by the track/ss pin: 1. tying track/ss to sv in selects the internal soft-start circuit. this circuit ramps the output voltage to the final value within 1ms. 2. if a longer soft-start period is desired, it can be set ex - ternally with a resistor and capacitor on the tr ack/ss figure 3. load step transient forced continuous mode (avp inactive) v out 200mv/div i l 1a/div 50s/div 3612 f03 v in = 3.3v v out = 1.8v i load = 100ma to 3a v mode = 1.5v compensation figure 1 v out 100mv/div i l 1a/div 50s/div 3612 f04 v in = 3.3v v out = 1.8v i load = 100ma to 3a v mode = 1.5v v ith = 3.3v output capacitor value figure 1
ltc3612 0 3612fa a pplica t ions i n f or m a t ion pin, as shown in figure 1. the track/ss pin reduces the value of the internal reference at v fb until track/ss is pulled above 0.6v. the external soft-start duration can be calculated by using the following formula: t s s = r s s ? c s s ? l n s v i n s v i n ? 0 . 6 v ? ? ? ? ? ? 3. the track/ss pin can be used to track the output voltage of another supply. each time the run pin is tied high and the ltc3612 is turned on, the track/ss pin is internally pulled down for ten microseconds in order to discharge the external capacitor. this discharging time is typically adequate for capacitors up to about 33nf. if a larger capacitor is required, connect the external soft-start resistor to the run pin. regardless of either internal or external soft-start state, the mode pin is ignored and soft-start will always be in pulse-skipping mode. in addition, the pgood pin is kept low and foldback of the switching frequency is disabled. output voltage tracking input if the ddr pin is not tied to sv in , once v track/ss exceeds 0.6v, the run state is entered and the mode selection, power good and current foldback circuits are enabled. in the run state, the track/ss pin can be used for track - ing down/up the output voltage of another supply. if the v track/ss drops below 0.6v, the ltc3612 enters the down tracking state and v out is referenced to the track/ss volt - age. if the track/ss pin drops below 0.2v, the switching frequency is reduced to ensure that the minimum duty cycle limit does not prevent the output from following the track/ss pin. the run state will resume if v track/ss again exceeds 0.6v and v out is referenced to the internal precision reference (see figure 7). through the track/ss pin, the output voltage can be set up for either coincident or ratiometric tracking, as shown in figure 5. figure 5. two different modes of output voltage tracking time (5b) ratiometric tracking v out1 v out2 output voltage time 3612 f05 (5a) coincident tracking v out1 v out2 output voltage to implement the coincident tracking behavior in fig - ure 5a, connect an extra resistive divider to the output of the master channel and connect its midpoint to the track/ss pin for the slave channel. the ratio of this divider should be selected to be the same as that of the slave channels feedback divider (figure 6a). in this track - ing mode, the master channels output must be set higher than slave channels output. to implement the ratiometric tracking behavior in figure 5b, different resistor divider values must be used as specified in figure 6b. for coincident start-up, the voltage value at the track/ss pin for the slave channel needs to reach the final reference value after the internal soft-start time (around 1ms). the master start-up time needs to be adjusted with an external capacitor and resistor to ensure this.
ltc3612 3612fa a pplica t ions i n f or m a t ion external reference input (ddr mode) if the ddr pin is tied to sv in (ddr mode), the run state is entered when v track/ss exceeds 0.3v and tracking down behavior is possible if the v track/ss voltage is below 0.6v. this allows track/ss to be used as an external reference between 0.3v and 0.6v if desired. during the run state in ddr mode, the power good window moves in relation to the actual track/ss pin voltage if the voltage value is between 0.3v and 0.6v. note: if track/ss voltage is 0.6v, either the tracking circuit or the internal reference can be used. during up/down tracking the output current foldback is disabled and the pgood pin is always pulled down (see figure 8). efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) figure 6a. set-up for coincident tracking figure 6b. set-up for ratiometric tracking v fb2 r4 r2 r4 r2 r3 r2 r4 r3 v out2 v out1 ltc3612 track/ss2 v fb1 v in ltc3612 ltc3612 channel 2 slave ltc3612 channel 1 master track/ss1 3612 f06a v fb2 r1 r2 r5 r6 r3 r1/r2 < r5/r6 r4 v out2 v out1 ltc3612 track/ss2 v fb1 v in 3612 f06b ltc3612 ltc3612 channel 2 slave ltc3612 channel 1 master track/ss1 where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is usually of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in due to gate charge, and it is typically larger than the dc bias current. both the dc bias and gate charge losses are proportional to v in ; thus, their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor, r l . in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance character - istics curves. to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss.
ltc3612 3612fa a pplica t ions i n f or m a t ion figure 7. ddr pin not tied to s vin figure 8. ddr pin tied to sv in . example ddr application soft-start state t ss > 1ms shutdown state 0.6v 0.6v 0.2v 0v 0v 0v 0v v in v in v fb pin voltage track/ss pin voltage run pin voltage sv in pin voltage run state run state time 3612 f07 reduced switching frequency down tracking state up tracking state soft-start state t ss > 1ms shutdown state 0.3v 0.45v 0.45v 0.3v 0.2v 0v 0v 0v 0v v in v in v fb pin voltage external voltage reference 0.45v track/ss pin voltage run pin voltage sv in pin voltage run state run state time 3612 f08 reduced switching frequency down tracking state up tracking state
ltc3612 3612fa thermal considerations in most applications, the ltc3612 does not dissipate much heat due to its high efficiency. however, in applications where the ltc3612 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 160c, both power switches will be turned off and the sw node will become high impedance. to prevent the ltc3612 from exceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by: t rise = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t rise where t a is the ambient temperature. as an example, consider the case when the ltc3612 is in dropout at an input voltage of 3.3v with a load current of 3a at an ambient temperature of 70c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the p - channel switch is 0.075. therefore, power dissipated by the part is: p d = (i out ) 2 ? r ds(on) = 675mw for the qfn package, the ja is 43c/w. therefore, the junction temperature of the regulator operat - ing at 70c ambient temperature is approximately: t j = 0.675w ? 43c/w + 70c = 99c we can safely assume that the actual junction temperature will not exceed the absolute maximum junction tempera - ture of 125c. note that for very low input voltage, the junction tempera - ture will be higher due to increased switch resistance, r ds(on) . it is not recommended to use full load current for high ambient temperature and low input voltage. to maximize the thermal performance of the ltc3612 the exposed pad should be soldered to a ground plane. see the pcb layout board checklist. design example as a design example, consider using the ltc3612 in an application with the following specifications: v in = 2.25v to 5.5v, v out = 1.8v, i out(max) = 3a, i out(min) = 100ma, f = 2.6mhz. efficiency is important at both high and low load current, so burst mode operation will be utilized. first, calculate the timing resistor: r t = 3 . 8 2 ? 1 0 1 1 h z 2 . 6 m h z ? ? 1 6 k ? = 1 3 0 k ? next, calculate the inductor value for about 30% ripple current at maximum v in : l = 1 . 8 v 2 . 6 m h z ? 1 a ? ? ? ? ? ? ? 1 ? 1 . 8 v 5 . 5 v ? ? ? ? ? ? = 0 . 4 6 6 h using a standard value of 0.47h inductor results in a maximum ripple current of: ? i l = 1 . 8 v 2 . 6 m h z ? 0 . 4 7 h ? ? ? ? ? ? ? 1 ? 1 . 8 v 5 . 5 v ? ? ? ? ? ? = 0 . 9 9 a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, a 68f (or 47f plus 22f) ceramic capacitor is used with a x5r or x7r dielectric. a pplica t ions i n f or m a t ion
ltc3612 3612fa c in should be sized for a maximum current rating of: i r m s = 3 a ? 1 . 8 v 3 . 6 v ? 3 . 6 v 1 . 8 v ? 1 ? ? ? ? ? ? = 1 . 5 a r m s decoupling the pv in with two 22f capacitors, is adequate for most applications. if we set r2 = 196k, the value of r1 can now be determined by solving the following equation. r 1 = 1 9 6 k ? 1 . 8 v 0 . 6 v ? 1 ? ? ? ? ? ? a value of 392k will be selected for r1. finally, define the soft start-up time choosing the proper value for the capacitor and the resistor connected to track/ss. if we set minimum t ss = 5ms and a resistor of 2m, the following equation can be solved with the maximum sv in = 5.5v : c s s = 5 m s 2 m ? i n 5 . 5 v 5 . 5 v ? 0 . 6 v ? ? ? ? ? ? = 2 1 . 6 n f the standard value of 22nf guarantees the minimum soft-start up time of 5ms. figure 1 shows the schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3612: 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3612. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin, and the (C) terminal as close as possible to the exposed pad, pgnd. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small-signal nodes. 4. flood all unused areas on all layers with copper. flood - ing with copper will reduce the temperature rise of power components. connect the copper areas to pgnd (exposed pad) for best performance. 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd. a pplica t ions i n f or m a t ion
ltc3612 3612fa typical a pplica t ions general purpose buck regulator using ceramic capacitors, 2.25mhz run track/ss rt/sync pgood ith pgood sgnd pgnd v in 2.25v to 5.5v pv i n _drv ddr sv in ltc3612 sw pv in c f 1f r f 24 l1 470nh r1 392k c3 22pf r2 196k 3612 ta02a mode v fb c o1 47f c o2 22f c c1 10pf c1 22f c2 22f c c 220pf c ss 10nf v out 1.8v 3a r4 100k r5b 1m l1: vishay ihlp-2020bz 0.47h r5a 1m r c 43k r ss 4.7m efficiency vs output current load step response in forced continuous mode output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3612 ta02b 0 10 v in = 2.5v v in = 3.3v v in = 4v v in = 5.5v v out 100mv/div i out 1a/div 20s/div 3612 ta02c v in = 3.3v v out = 1.8v i out = 100ma to 3a v mode = 1.5v
ltc3612 3612fa typical a pplica t ions master and slave for coincident tracking outputs using a 1mhz external clock run track/ss rt/sync pgood ith pgood sgnd pgnd v in 2.25v to 5.5v pv i n _drv ddr sv in ltc3612 sw pv in c f1 1f r f1 24 l1 1h channel 1 master channel 2 slave r1 715k c3 22pf r2 357k r3 464k r4 464k 3612 ta03a mode v fb c o11 47f c o12 22f c c2 10pf c1 22f c2 22f c c1 470pf v out1 1.8v 3a 10nf 4.7m 4.7m 4.7m r5 100k 1mhz clock r c1 15k run track/ss rt/sync pgood ith pgood sgnd pgnd pv i n _drv ddr sv in ltc3612 sw pv in c f2 1f r f2 24 l2 1h r5 301k c7 22pf r6 301k mode v fb c o21 47f c o22 22f c c4 10pf c6 22f c5 22f c c3 470pf v out2 1.2v 3a r7 100k r c2 15k coincident start-up coincident tracking up/down 500mv/div 2ms/div 3612 ta03b v out1 v out2 500mv/div 200ms/div 3612 ta03c v out1 v out2
ltc3612 3612fa p ackage descrip t ion udc package 20-lead plastic qfn (3mm 4mm) (reference ltc dwg # 05-08-1742 rev ?) 3.00 0.10 1.50 ref 4.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 s 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udc20) qfn 1106 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.50 ref 3.10 0.05 4.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline r = 0.05 typ 1.65 0.10 2.65 0.10 1.65 0.05 2.65 0.05 0.50 bsc
ltc3612 3612fa p ackage descrip t ion fe package 20-lead plastic etssop (4.4mm) (reference ltc dwg # 05-08-1663 rev g) exposed pad variation cb fe20 (cb) etssop rev g 0510 0.09 ? 0.20 (.0035 ? .0079) 0 o ? 8 o 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 p 0.05 0.65 bsc 4.50 p 0.10 6.60 p 0.10 1.05 p 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc3612 3612fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 08/10 updated temperature range in order information 2 edited electrical characteristics table and updated note 2 3, 4 updated text in graphs g19, g31 7, 9 updated pin 16/pin 3 and pin 21/pin 21 text 10 updated functional block diagram 11 updated burst mode operationexternal clamp section 13 updated internal and external compensation section 18 updated soft-start section 19 updated timing resistor equation in design example section 23 updated ta02a and ta02c in typical applications 25 updated related parts 30
ltc3612 0 3612fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0810 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion ddr termination with ratiometric tracking of v dd , 1mhz ratiometric start-up part number description comments ltc3614 5.5v, 4a (i out ), 4mhz, synchronous step-down dc/dc converter with tracking and ddr 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 5mm qfn-24 package ltc3616 5.5v, 6a (i out ), 4mhz, synchronous step-down dc/dc converter with tracking and ddr 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 5mm qfn-24 package ltc3601 15v, 1.5a (i out ), synchronous step-down dc/dc converter 95% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 1a, msop-16e and 3mm 3mm qfn-16 packages ltc3603 15v, 2.5a, synchronous step-down dc/dc converter 92% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-16 package ltc3605 15v, 5a (i out ), synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 15v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 package ltc3412a 5.5v, 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, tssop-16e and 4mm 4mm qfn-16 packages ltc3413 5.5v, 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% efficiency, v in : 2.25v to 5.5v, v out(min) = v ref /2, i q = 280a, i sd < 1a, tssop-16e package run track/ss rt/sync pgood pgood sgnd pgnd v in 3.3v v dd 1.8v pv i n _drv ddr sv in ltc3612 sw pv in l1 1h r1 200k c3 22pf r2 200k 3612 ta04a mode v fb c4 100f c5 47f c c1 10pf c2 22f c1 22f c c 2.2nf v tt 0.9v 1.5a r3 100k r8 365k r5 1m l1: coilcraft do3316t r4 1m r c 6k r7 187k r6 562k ith 500mv/div 500s/div 3612 ta04b v dd v tt

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